Although the element size of transistors is decreased in accordance with technology scaling such as Moore's Law, there has been no corresponding scaling of the local wiring delay inside semiconductor chips. Short gate length technology is used for high-speed operation inside semiconductor chips. Consequently, the proportion of the capacitance of wiring included in the output capacitance of a gate is increased and has a greater influence than the input capacitance of a subsequent gate. Power consumed by driving of wiring is increased and power efficiency at the time of data transmission is degraded.
Voltage mode complementary metal oxide semiconductor (CMOS) drivers and current driving current mode logic (CML) drivers are used in transmission systems employed inside semiconductor chips. For either type of driver, after deciding upon fan-out, which expresses a relationship between a driving power and a load, data transmission is performed via a plurality of repeaters.
The related art are disclosed in Japanese Laid-open Patent Publication No. H10-224270 and Japanese Laid-open Patent Publication No. 2009-55306.